SiC 8-inch Wafer Supply System

The transition to 8-inch is a question of "who" and "at what scale," not "when."

The substrate diameter for SiC power semiconductors is currently shifting from 6-inch (150mm) to 8-inch (200mm). However, there is still a significant gap between the fact that "the transition has begun" and the fact that "a stable supply system is in place." When evaluating the supply system for 8-inch substrates from a design and procurement perspective, the structural question of "who can supply, at what production scale, and at what quality level" is more important than the transition timeline.

The current 8-inch SiC substrate market is in the development and mass production preparation stage by a few suppliers. While companies like Wolfspeed, Coherent (formerly II-VI), and SiCrystal are working on 8-inch wafer production, securing yields and ensuring crystal quality uniformity is more challenging compared to 6-inch, and mass production costs remain high. Mitsubishi Electric's strengthened joint development partnership with Coherent for 8-inch SiC substrates, advancing their efforts to secure substrates for their new factory in Kumamoto, exemplifies this competition.

The linkage between "substrate quality" and "device specifications" cannot be overlooked when examining the supply system. While an 8-inch wafer can yield approximately 1.8 times more chips than a 6-inch wafer, an increase in crystal defect density, such as micropipes, can reduce the effective supply capacity even with more chips, due to lower yields. In procurement decisions, it is crucial to verify not only the "8-inch compatible" label but also the defect density specifications and the reality of yield guarantees as deciding factors.

Who can mass produce 8-inch wafers — The difference in supplier capabilities

When discussing the supply system for 8-inch SiC substrates, "developed," "mass-producible," and "stably supplied" are entirely different stages. Currently, most suppliers are in the "developed or preparing for mass production" stage, and stable supply to device manufacturers has only truly begun for a limited number of companies and part numbers.

The collaboration between Mitsubishi Electric and Coherent is a prime example. Their move to secure high-quality 8-inch substrates for the Kumamoto factory indicates that device manufacturers are beginning to adopt an approach of "jointly developing and securing supply with suppliers" rather than simply "procuring from the market." This scenario signifies that wafer procurement is transforming from a simple purchasing transaction to a strategic partnership.

Wolfspeed has announced plans to operate a large-scale 8-inch wafer manufacturing facility in North Carolina, USA, in 2024, aiming for first-mover advantage in terms of scale. Meanwhile, Coherent, along with SiCrystal, is positioned to capture demand from Europe and Japan. The geographical distribution of suppliers is directly linked to the geopolitical aspects of supply risk.

These evaluation criteria serve as common points of confirmation for both engineers selecting devices and procurement personnel selecting suppliers. The "relationship with device manufacturers" in particular influences the wafer suppliers' capacity for open market supply, indirectly affecting the supply risk of finished devices.

From 6-inch to 8-inch — The true change in cost

The most frequently cited benefit of transitioning to 8-inch is the reduction in chip cost. The logic that the cost per chip decreases due to the increased number of usable chips per wafer is correct. However, for this calculation to hold true, the prerequisite is that "yield comparable to 6-inch can be achieved with 8-inch."

The cost of 6-inch SiC wafers has gradually decreased with the expansion of mass production in recent years. 8-inch production is more challenging, and currently, the wafer unit price is said to be around double that of 6-inch. However, when viewed on a per-chip area basis, the cost may fall below that of 6-inch if yields stabilize. "When this crossover occurs" will be a turning point for decisions at all levels: design, procurement, and business planning.

This graph is a reference based on approximate area ratios. It indicates that the transition from 6-inch to 8-inch nearly doubles the number of chips obtained. The actual supply effect will be determined by multiplying this by the yield rate and defect density. Instead of concluding that "8-inch is advantageous" solely based on cost, confirming the actual yield situation with suppliers will lead to more realistic procurement decisions.

There are also issues with manufacturing equipment. The transition to 8-inch SiC requires not only wafer manufacturing but also the 8-inch compatibility of equipment and fixtures in the device manufacturing process. For device manufacturers who have invested in existing 6-inch lines, switching to 8-inch involves additional investment, and the prospect of recovering this investment will be the key to investment decisions.

Impact on device design — Selection criteria changed by 8-inch substrates

Changes in wafer diameter also affect device design. The performance parameters of SiC MOSFETs—particularly the trade-off between short-circuit withstand time (SCWT) and on-resistance (Ron)—are closely linked to substrate quality and manufacturing process precision.

Short-circuit withstand time is the time a device can withstand a load short circuit before failing, and it is a critical parameter for determining the margin of protective circuit design. SiC, with its smaller die and higher current density compared to silicon, heats up quickly, imposing stricter requirements on the response time design of protective circuits. Microchip's 1200V rated SiC MOSFETs specify a typical value of 3μs under specific conditions in their datasheets. This figure dictates the design margin for protective circuits, and the selection of a gate driver cannot be considered independently of short-circuit withstand time.

The trade-off between short-circuit withstand time and Ron is expected to improve with enhanced substrate quality through 8-inch scaling, enabling more precise structural design. Mitsubishi Electric has significantly improved short-circuit withstand time by introducing a p-type protective layer in their trench SiC-MOSFETs, and Rohm has achieved both low Ron and high short-circuit withstand time in their 4th generation SiC MOSFETs through proprietary structures. Both of these represent advancements in device structures that are only possible with improvements in upstream substrate quality.

As 8-inch substrates become more widespread, the scope for improving these trade-offs may further broaden. However, individual differences and lot variations in substrate quality will directly translate to device characteristic variability, requiring the evaluation of mass production stability to be incorporated from the design stage.

"Co-design" with protective circuits

With the maturation of the 8-inch substrate supply system, the application areas for SiC devices will expand. However, the difficulty of implementing SiC lies not just in selecting the device but in its overall integration. Short-circuit protection design only becomes meaningful when the device's individual specifications and the protective circuit's parameter settings function as a unified system.

DESAT (desaturation) protection is a method that monitors the drain-source voltage in the on-state and turns off the transistor when overcurrent is detected. It is widely used for SiC MOSFET short-circuit protection. The three key design parameters are the DESAT trigger threshold (V_DESAT), DESAT current (I_DESAT), and the short-circuit blanking time.

Blanking time is a dead zone implemented to prevent false detection during switching. However, if this time is too long, damage to the device can accumulate. Considering that SiC's short-circuit withstand time is on the order of a few microseconds, setting the blanking time requires particular caution. Understanding the condition dependency of short-circuit withstand time—drain voltage, gate voltage, and junction temperature—is the starting point for ensuring reliability by securing a design margin that accounts for worst-case operation.

What to confirm regarding the supply system in the 8-inch era

When evaluating the supply system for 8-inch SiC substrates, organizing the "items to confirm" at the current stage reveals different questions at the technical, procurement, and business levels.

At the technical level, it is beneficial to understand whether the device under consideration for adoption is derived from 6-inch or 8-inch substrates. Characteristic variations and lot-to-lot differences depend on the substrate lot and manufacturing conditions. Therefore, at the transition point of substrate diameter, confirming whether the evaluation samples and mass-produced products are from the same substrate generation will affect the accuracy of design margin estimation.

At the procurement level, the supplier's 8-inch transition roadmap and the duration of current 6-inch supply continuation serve as decision factors. The timing of the reduction in 6-inch product manufacturing as the shift to 8-inch progresses is also relevant to the extension plan of existing designs. Onsemi offers a broad portfolio covering SiC MOSFETs, diodes, and modules from 650V to 1700V. The supply continuity for such a supplier with a wide product line as they transition to 8-inch can be viewed as the stability of the entire portfolio.

At the business and investment level, the question arises as to when the cost crossover point for 8-inch wafers will occur. The prospect of recovering capital investment, the existence of long-term contracts with major customers, and the progress of wafer suppliers' capital strength and capacity expansion investments—these factors collectively shape the reality of a "stable supply system." The extent to which joint development alliances like Mitsubishi Electric and Coherent will expand is a structural variable that influences the availability of 8-inch SiC substrates in the open market and is worth continuing to monitor.