Navigating SiC Wafer Procurement Risks

Understanding SiC Wafer Procurement Risks Starts with Knowing Where Bottlenecks Occur

With the widespread adoption of SiC (silicon carbide) power semiconductors, stable procurement of wafers themselves is increasingly becoming the biggest bottleneck after design completion. No matter how excellent a device is chosen during the design phase, mass production cannot proceed without wafers. To manage procurement risks, the starting point for decision-making is to structurally understand "in which process and in what way bottlenecks occur."

The fundamental difference between SiC wafer supply chains and those for silicon lies in the fact that SiC is a material that is "difficult to manufacture" from raw materials to substrates. Unlike silicon's Czochralski method, which pulls from a liquid phase, SiC cannot be produced this way. Instead, single crystals are slowly grown in millimeter increments using the sublimation method (PVT method) at temperatures exceeding 2000°C, and then sliced into wafers. The growth rate is a fraction of that for silicon, and this physical constraint is the fundamental reason for the reduced flexibility of the entire supply chain.

How Wafer Quality Connects to Device Characteristics

When discussing SiC wafers, the metric that cannot be avoided is "defect density." The density of micropipes (through-defects), stacking faults (SF), and dislocations within the crystal directly impacts device yield and reliability. Particularly for 4H-SiC used in power devices, fewer of these defects lead to more stable dielectric breakdown strength and more predictable device behavior during short circuits.

When "short-circuit withstand time (SCWT)" is discussed in the selection of SiC MOSFETs, its value is influenced not only by the device structure but also by the defect state of the substrate.

SCWT is the time until the device fails during a load short circuit and corresponds to the margin of time before the protection circuit operates. For Microchip's 700V/1200V products, the datasheet specifies a typical value of 3μs, which serves as the reference for protection circuit design. However, this value is dependent on measurement conditions.

As the conditions of drain voltage, gate voltage, and junction temperature are relaxed, the withstand time tends to increase. This means the datasheet figures should be read not as "guarantees under worst-case conditions" but as "representative values under specific conditions." If the quality of wafers from a supplier varies from lot to lot, the withstand time after implementation may fluctuate even for the same component, which becomes the point of contact between wafer procurement risk and device reliability.

Why SiC is More "Prone to Bottlenecks" Than Si

Comparing the supply chains of silicon power devices and SiC devices clearly reveals where SiC's vulnerability lies.

Of these four factors, the "transition period risk" is particularly impactful right now. Mitsubishi Electric's strengthening of its joint development partnership with Coherent for 8-inch SiC substrates can be interpreted as a move to secure high-quality substrates during this transition period. If suppliers who have not yet recovered their investment in 6-inch equipment adopt a cautious stance on 8-inch, it is likely that capacity will be left unused during the transition.

There are also differences in characteristics compared to silicon devices.

SiC dies are smaller and have higher current density than silicon. While this allows for more chips to be produced from the same wafer area, it also results in faster temperature rise when a short circuit occurs. This is why the response time of protection circuits must be shortened compared to the design standards of the silicon era. When wafer quality is unstable, there is a risk that the thermal margin will be narrower than the design margin.

How Technological Evolution is Changing the Risk Map

When considering wafer procurement risks, it is essential not to overlook the impact of structural improvements in devices on supplier selection. The trade-off between short-circuit withstand capability and on-resistance (Ron) has long been a challenge for SiC MOSFETs, but companies are moving towards mitigating this relationship through structural improvements.

Mitsubishi Electric has significantly improved short-circuit withstand capability by introducing a p-type protective layer in its trench SiC-MOSFETs. ROHM's fourth-generation SiC MOSFETs aim to achieve both low on-resistance (RonA) and high short-circuit withstand capability through their proprietary device structure. To benefit from these improvements, it is a prerequisite that wafer quality is at a level that supports these structures. In other words, the more advanced the structural improvements, the greater the dependence on "good wafers."

Since the influence of each condition varies by device, always compare the measurement conditions in datasheets and application notes.

There is an interesting relationship regarding temperature dependency. At higher temperatures, RDSon increases, limiting saturation current, so SiC MOSFETs tend to have improved short-circuit withstand capability at higher temperatures. This is a different characteristic from silicon IGBTs, and the estimation of operating temperature directly impacts the accuracy of protection design.

In protection circuit implementation, the DESAT (desaturation) function plays a central role. It monitors the drain-source voltage (VDS) in the on-state and turns off the power transistor when overcurrent is detected. To ensure this protection circuit functions properly, parameters such as VDESAT (DESAT trigger threshold), IDESAT (DESAT current), and short-circuit blanking time need to be optimized.

Correctly setting these parameters requires not only the datasheet of the device being adopted but also actual measured values under implementation conditions. If wafer quality varies from lot to lot, there is a risk that protection operation will become unstable with the same parameter settings. From this perspective, considering not only the catalog specifications but also the wafer quality management system of the supplier improves the accuracy of device selection.

What to Check from Suppliers Then

Translating wafer procurement risk into practical terms leads to the question: "Which suppliers are implementing what level of quality control?" Organizing this from both technical superiority and procurement stability reveals what needs to be checked.

onsemi offers a complete portfolio including SiC MOSFETs, SiC diodes, and SiC modules from 650V to 1700V, touting system efficiency improvements due to low power loss with their EliteSiC brand devices. Infineon, on the other hand, covers similar voltage ranges with its CoolSiC series and emphasizes an ecosystem combined with gate drivers. For such major players, whether they manufacture wafers in-house or, if not, which wafer suppliers they have long-term supply agreements (LTAs) with, serves as a determinant of procurement stability.

The primary applications and competitive landscape differ depending on the voltage rating. 1200V products are experiencing the most rapid surge in demand for EV inverters and industrial converters, making it the most fiercely competitive band for procurement. 650V products follow in demand, with ongoing replacement competition against silicon SJ-MOSFETs.

Specific confirmation items that provide clues for judgment include: the ratio of in-house wafer production versus external procurement, the status of long-term supply agreements (LTAs), quality assurance standards (compliance with AEC-Q101 and MTBF figures), and the roadmap for wafer diameters during the transition period (switchover timing from 6-inch to 8-inch). These serve as materials for reliability evaluation for designers and as grounds for negotiation for procurement personnel.

From both technical and business perspectives, SiC wafer procurement risk can be divided into the short-term question of "can I get the current lot?" and the medium-term question of "will there be a stable supply when mass production starts in 2-3 years?" The former is influenced by the spot market situation, while the latter is influenced by supplier capital investment and wafer roadmaps. The type of information to be checked also changes depending on which timeframe is used to view the risk. SiC wafer procurement risk management is an area within semiconductor procurement that particularly demands "the ability to read supplier technology roadmaps."