On October 8, 2026, Infineon Technologies unveiled a 27 kW three-phase power supply unit (PSU) reference design for AI servers. It targets server ODMs and OEMs and meets the requirements of the Open Compute Project (OCP) Open Rack V3 (ORV3) specification and AI server rack architectures.
Infineon framed the launch against the shift toward 800 VDC or ±400 VDC power architectures driven by rising GPU performance and rack density. By offering a complete PSU reference design rather than components alone, it aims to shorten development time for ODMs and OEMs.
Key specifications
Efficiency
Peak above 98% (480 VAC, 50% load). Five-level ANPC PFC and three-level LLC converter.
Power density
116 W/in³. The ORV3 minimum is 94 W/in³.
Input range
Three-phase 311–528 VAC. Power factor above 0.99 across most of the load range; operating ambient -5 to 45°C.
Load transients
20 ms hold-up. Smooths input voltage during sudden GPU load changes and eliminates the CBU.
SiC and Si side by side in one supply
Every component is from Infineon. The power stage combines 650 V CoolSiC MOSFETs with CoolMOS MOSFETs (silicon), alongside EiceDRIVER gate drivers, XENSIV current sensors and a PSOC microcontroller. Handling a three-phase 480 VAC input with 650 V devices is possible because the design uses multilevel circuits: five levels in the PFC and three in the LLC.
Both the PFC and LLC stages are digitally controlled. A programmable power control accelerator (PPCA) integrated into the PSOC Control C3 Performance Line microcontroller regulates current and voltage to follow sudden swings in AI workloads. An integrated planar magnetic structure keeps the high-frequency transformer compact and modular.
How to split GaN and SiC in AI server power has become a design question in its own right; this reference design pairs 650 V-class SiC with silicon superjunction MOSFETs.
Moving the capacitor bank inside the PSU
The detail with the biggest practical impact is that load-transient handling has moved inside the PSU. Sudden GPU load changes make the rack's input voltage fluctuate. Some configurations have absorbed this with a separate capacitor bank unit (CBU). In Infineon's reference design, the integrated energy buffer takes over that role and also rides through short grid disturbances with 20 ms of hold-up.
Rack space allocation keeps being rethought, as with OCP's Diablo concept that moves rack power into a dedicated sidecar. Eliminating the CBU frees that space for PSUs or compute.
What it means for design and procurement
- Another ORV3 reference design: published targets for power density and efficiency give ODMs a benchmark to compare their own designs against
- Wide input range: support for three-phase 311–528 VAC reduces the need for region-specific power designs
- These are reference design figures: pricing and design wins for production units have not been disclosed. Infineon will show the hardware at OCP Global Summit 2026 (October 12–15, San Jose, California, booth E26) and at OktoberTech Silicon Valley 2026 on October 22