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Advanced Packaging

Advanced Packaging

The main battleground for AI-chip performance has shifted from front-end scaling to back-end packaging. We read CoWoS/HBM and chiplets, the tightening ABF and glass substrate supply, and the equipment / material / OSAT chains through primary sources such as TSMC, Intel, SK hynix and JEDEC — without over-weighting any single country.

Articles

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News

CoWoS/2.5D Packaging: TSMC vs Intel

TSMC's CoWoS (2.5D) underpins AI accelerator performance and is expanding to automotive qualification, System-on-Wafer in 2027, and COUPE (CPO) in 2026. Intel is consolidating Foveros volume production, EMIB, and ASAT at Fab 9. We map the shift of the main battleground to back-end packaging with primary sources.

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The Rise of Glass Substrates: Intel and SKC

Organic substrates approach their scaling limit by the end of the decade. The next move is glass. After a decade of research, Intel heads toward the 2030s, raising interconnect density and multi-chiplet integration with ultra-low flatness. SKC (Absolics) completed the world's first volume facility in Georgia, USA — 40% faster, with a $75M subsidy. We map the next-gen substrate for AI back-end.

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HBM4: Supply Chain and JEDEC Standard

SK hynix completed HBM4 development in September 2025, doubling bandwidth, improving power efficiency by 40%, and adopting 2,048 I/O. The JEDEC standard JESD270-4 defines 2 TB/s and 32 channels. Micron ramps 2.8 TB/s, 36GB 12H in 2026 and samples 48GB 16H. We map the supply chain and standard for HBM4, the star of AI memory.

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