HBM4 Enters Volume — SK hynix and Micron Supply, and the JEDEC Standard That Sets AI Memory's Next Stage

HBM, the star of AI memory, moves to the next generation

AI accelerator performance is not decided by the speed of compute logic alone. How much bandwidth you can feed that logic — that is, high-bandwidth memory (HBM) — has become the rate-limiting factor for performance. And that HBM is now transitioning from HBM3E to HBM4, entering volume production through 2026.

HBM4 is the demand driver of advanced packaging itself. 2.5D packaging like CoWoS exists precisely to stack multiple layers of HBM beside the compute die. HBM4's supply and standard developments therefore move the demand and design constraints of the entire back end.

SK hynix — world-first HBM4 development completed

On September 12, 2025, SK hynix announced completion of HBM4 development and mass-production readiness. On performance, it doubled bandwidth, improved power efficiency by more than 40%, and doubled I/O terminals to 2,048 versus the prior generation. Operating speed exceeds 10 Gbps, above the 8 Gbps that the JEDEC standard defines.

Packaging technology underpins the ramp. HBM4 adopts Advanced MR-MUF and a 1bnm-class DRAM process. Advanced MR-MUF is an HBM volume-production technology focused on controlling warpage of the stacked chips and reducing the pressure applied to them. In HBM, which stacks many thin DRAM layers, managing warpage and stress determines yield and reliability. This is a domain where packaging technology directly governs memory performance.

JEDEC — the standard sets the foundation

Beyond individual companies' technology, an industry standard sets HBM4's foundation. JEDEC published the HBM4 standard, JESD270-4, providing a basis for interoperability. The key points are clear: it delivers up to 2 TB/s over a 2048-bit interface and doubles independent channels per stack from 16 to 32. DRAM stacks are supported from 4-high to 16-high, giving latitude in scaling capacity and bandwidth.

A standard that allows a wide range of configurations means memory makers can differentiate on capacity and stack height while the system side retains compatibility. For procurement, this reads as: every vendor's HBM4 sits on the same standard foundation — but yield, stack height, and supply volume set them apart.

Micron — the U.S. maker's volume ramp

HBM is contested by three makers — SK hynix, Samsung, and Micron — and the U.S.-based Micron also shows presence in volume. Micron's HBM4 operates above 11.0 Gbps and delivers over 2.8 TB/s per stack. It ramps 36GB 12-high for next-gen AI and HPC in 2026 and supplies 48GB 16-high samples to customers to push capacity higher. Power efficiency improves 20% versus HBM3E 12-high.

That supply is not concentrated in a single country matters for buyers. HBM4 runs in parallel across Korean makers (SK hynix, Samsung) and the U.S. maker (Micron), with the standard (JEDEC) laying a compatible foundation.

Reading supply and design constraints

Business impact and checkpoints

From a procurement and investment view: (1) which vendor's HBM4 the AI accelerator you adopt depends on, and whether its supply volume and stack height (12H/16H) are secured; (2) whether the HBM4 ramp tightens in tandem with 2.5D packaging capacity such as CoWoS; and (3) within the capacity and stack-height latitude the standard (JESD270-4) allows, how vendors differentiate on yield and power efficiency. HBM4 is not merely a memory generation change — it is worth tracking as a junction that moves AI-chip performance and back-end demand at the same time.

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