Cost remains the greatest barrier to widespread adoption of SiC and GaN devices. As of 2025, SiC MOSFETs are priced at 3–5x the equivalent Si IGBT. However, as 8-inch SiC wafer volume production ramps up and yield improvements progress, this cost gap is on a narrowing trend. GaN-on-Si can leverage existing Si manufacturing lines, so it is expected to achieve price competitiveness earlier than SiC. We examine the cost roadmap toward the 2030s and the current state of the manufacturing technologies that will determine it.
The Structural Cost Difference Between SiC and Si — Why Is It Expensive?
SiC (Silicon Carbide) wafer manufacturing is fundamentally different from silicon. Silicon wafers can be grown as single-crystal ingots using the Czochralski method, with mass production established up to 12-inch wafers. SiC wafers, by contrast, are primarily grown via PVT (Physical Vapor Transport), a process with growth rates of only a few hundred micrometers per hour — requiring days to weeks to produce wafers of just a few inches in diameter. This difference in manufacturing time is the root cause of the wafer cost premium over silicon.
SiC wafers are also difficult to control for crystal defects (TEDs, SFs, MPDs, etc.), with a significant impact on yield. Device manufacturing further requires dedicated equipment capable of handling high-temperature processes, rather than simply reusing silicon manufacturing lines. These factors combine so that SiC device manufacturing costs can be 5–10x those of silicon in some cases.
Three Drivers of SiC Cost Reduction
Transition to 8-Inch Wafers
The increase in wafer area (approximately 1.8x compared to 6-inch) increases the number of chips obtained per manufacturing run. Wolfspeed began full-scale 8-inch production in 2024, with other manufacturers expected to follow between 2026 and 2027. The manufacturing cost reduction effect from 8-inch conversion alone is estimated at 20–30%, and a 30–40% reduction is expected when combined with yield improvement.
Reduction of Crystal Defect Density
Threading edge dislocations (TEDs), stacking faults (SFs), and micropipes (MPDs) specific to SiC wafers are major determinants of device yield. Defect density is being reduced through improvements in the epitaxial growth process and substrate quality improvement, and yield improvement translates directly to cost reduction. Major manufacturers are continuing quality improvement efforts targeting MPD densities below 0.1 per cm².
Dedicated and Automated Manufacturing Lines
SiC-dedicated high-temperature oxidation furnaces (above 1,200°C), ion implantation equipment, and grinding and polishing equipment are becoming more widespread. The shift from mixed-flow with general Si manufacturing lines to dedicated lines reduces changeover losses and delivers cost improvement through quality stabilization. Automated wafer handling improvements also contribute to yield enhancement.
GaN-on-Si Cost Advantage
GaN-on-Si can leverage existing 8-inch Si manufacturing lines, giving it a substantially lower wafer cost baseline than SiC. While uniformity of epitaxial growth (within-wafer and wafer-to-wafer variation) had been a challenge, EPC, Navitas, and GaN Systems improved mass-production yields between 2024 and 2025. For applications below 650 V, GaN-on-Si costs are approaching those of Si MOSFETs.
The primary factors supporting GaN-on-Si cost reduction are:
- Leveraging existing Si manufacturing lines: Enables production scaling without major new capital investment
- 8-inch wafer compatibility: Larger wafer diameters have been achieved earlier than for SiC
- Improved epitaxial growth yield: Defect uniformity within wafers has improved, with an increasing number of manufacturers achieving yields above 85%
SiC MOSFET (1200 V)
As of 2025, 3–5x Si IGBT. Most forecasts indicate a range of 2–3x by 2028–2030 through 8-inch conversion and yield improvement. Price sensitivity for EV traction and large industrial inverter applications is low, and TCO-based SiC adoption is already viable. Long-term, a ratio below 2x Si IGBT is projected, but full cost parity is widely forecast to be post-2035.
GaN-on-Si MOSFET (650 V)
As of 2025, 1.5–2x Si MOSFET. Some forecasts suggest near-parity cost will be reached as early as 2027–2028 through volume expansion and yield improvement. For data center and communications power applications, TCO-based advantages already exist. When the benefit of passive component miniaturization from high switching frequencies is included, GaN is increasingly advantageous on a system cost basis.
Long-Term Outlook (2030s)
By the 2030s, the cost gap between SiC/GaN and Si is projected to shrink to less than half its current level, and in applications where energy efficiency requirements are stringent, silicon replacement will become the default. However, in general-purpose, low-voltage, low-cost applications, Si will remain mainstream, and differentiation based on device-specific application suitability will continue.
Chinese SiC Entrants as an Uncertainty Variable
A key uncertainty in the cost roadmap is the quality improvement and price pressure from Chinese-made SiC wafers. China is advancing domestic production of SiC materials and manufacturing equipment, and if the quality of exported products reaches an adequate level from 2027–2028 onward, downward pricing pressure on global SiC wafers could materialize.
Chinese-made SiC wafers are currently considered to fall short of Western-tier manufacturers (Wolfspeed, II-VI, etc.) at the highest crystal quality grades, but practical adoption is advancing for industrial and lower-voltage applications. BYD Semiconductor, TanKeBlue Semiconductor, and Shandong Tianyue are emerging as major players, building mass-production track records through supply to domestic Chinese EV makers.
Downward Price Pressure on Wafers
If Chinese 6-inch wafers enter the international market in earnest from 2028–2030 onward, the pricing leverage of Wolfspeed, Coherent (formerly II-VI), and others could diminish. Existing long-term wafer purchase agreements (such as the 10-year contracts between Wolfspeed and Renesas) serve in part as hedges against this risk.
Need for Quality Evaluation
When adopting Chinese-made SiC wafers, third-party evaluation of defect density and crystal quality is necessary. Quantifying the impact on device yield and long-term reliability is the starting point for procurement risk management.
Trade-Off with Geopolitical Risk
Under U.S.-China tensions, there is a risk of export controls on Chinese-made SiC wafers. A dual-sourcing strategy (Western + Chinese suppliers) distributes supply risk but doubles quality management costs — a factor that must be weighed carefully.
Implications for Procurement Professionals
Understanding the SiC and GaN cost roadmap is important for timing device adoption decisions. For designs currently using Si IGBT with a next-generation refresh scheduled for 2027–2028 or later, there is the option of planning for a design change when SiC migration costs have decreased. Conversely, for designs adopting SiC now, actively proceeding with adoption in applications where TCO-based economic viability holds (EVs and large industrial inverters requiring high efficiency) directly translates to competitive advantage.
This variable affects procurement cost projections, so continuous information gathering from suppliers is important. Establishing a venue to share supplier technology roadmaps once or twice a year — covering wafer cost trends, new product release plans, and quality improvement progress — directly improves the accuracy of procurement planning.