ASE (Advanced Semiconductor Engineering) announced on May 26, 2026 that it has developed what it calls the industry's first automated 310mm square (310mm x 310mm) panel-level packaging (PLP) production line. Targeting next-generation advanced packaging for AI data centers and HPC, the company plans to begin production in the first half of 2027.
Key Specifications
The new line handles 310mm square panels with a usable area of up to 96,100mm². Its advanced packaging platforms support line/space of 2/2µm for FOCoS and 8/8µm for FOCoS-Bridge. By moving from conventional round wafers to rectangular panels, ASE aims to increase the number of dies per panel and improve throughput.
Purpose of Panelization
Round wafers leave unusable area around the edge, while rectangular panels can use area more efficiently. Larger panels can increase die count and support integration of complex multi-die structures, making them especially effective for AI and HPC applications where package size and I/O density continue to grow. ASE emphasizes high-bandwidth, low-latency connections among chiplets, ASICs, and HBM, positioning PLP as a back-end manufacturing platform for those requirements.
Implications for Procurement and Design
Advanced packaging has become a critical process that affects AI accelerator performance, yield, and cost. If panel-level packaging ramps in production, it could change both capacity and cost structure for large multi-die packages. For teams involved in back-end procurement and package design, the planned production timing in the first half of 2027 and the applicability of the FOCoS platform family will be important factors in next-generation package selection.