onsemi introduced a new power device architecture called the Embedded Power Platform (EPP) on September 16, 2026. The company, headquartered in Scottsdale, Arizona, positions it as a platform spanning three verticals: automotive, industrial and AI data centre.
The heart of the announcement is not the power density figure. It is that the way the design is partitioned has changed.
Using the silicon wafer as the package substrate
EPP uses the silicon wafer itself as the foundation of the package. Multiple die are integrated into a single silicon device, so that electrical, mechanical and thermal characteristics are optimised simultaneously inside one architecture.
In practical terms this means the boundary of responsibility moves. Power device design has long separated die design from package and assembly design: the device maker supplies die and a standard package, and thermal and mechanical work is resolved at board or module level.
Once die and package are one, that division stops holding. Part of the thermal and mechanical design moves inside the device, leaving less room to adjust at system level. onsemi describes this as reducing design complexity, but complexity does not disappear — it relocates.
Up to 3–5x power density against current solutions
onsemi states that EPP achieves up to 3–5x the power density compared with existing power system designs. Integrating electrical, mechanical and thermal design from the earliest stage is what enables the improvement in system performance and the acceleration of development, according to the company.
That figure needs care. What is stated is a comparison against existing power *system* designs, not a device-to-device comparison. It is best understood as a comparison at the level of a system including package and assembly, and the number will shift depending on which baseline configuration is taken. Details of the conditions and benchmark used were not given in this announcement.
The direction is nonetheless consistent. In AI data centre power design and in the transition to 800VDC, the limiting factor has been less device performance than whether that performance can be extracted at the implementation level. An approach that reaches into the package addresses that constraint directly. The same concern runs through SiC module packaging technology.
Three vertical markets from one architecture
Automotive
Electrification and autonomous driving. The segment with the most demanding power requirements and reliability expectations.
Industrial
Industrial power supplies, motor drives and similar. A wide span of applications with dispersed requirements.
AI data centre
Power systems serving rapidly growing demand. Requirements for power density and efficiency are rising fastest here.
Covering three markets from a single architecture presumes scalability. Addressing multiple verticals with different power requirements using one design approach avoids fragmenting development investment.
At the same time, these three markets differ in required reliability levels, product lifetimes and certification frameworks. Tension remains: something designed for automotive requirements is over-specified for a data centre, while something optimised for data centre refresh cycles may not reach automotive lifetime requirements. How far the platform's generality holds in practice cannot be judged until individual design wins appear.
The questions design and procurement should hold
If architectures like EPP spread, what changes is less the performance number than design freedom and switching cost.
First, it is worth confirming where your own system-level differentiation sits. If you extract performance through thermal design and assembly craftsmanship, an architecture that absorbs that work into the device reduces your source of differentiation. If you have not been able to staff that work, you get the same performance for less effort.
Second, switching cost changes. A device where die and package are unified is harder to substitute. A standard package left an escape route through compatibility with other vendors' parts; a proprietary architecture does not. The axis of supply risk shifts from price and lead time to design portability.
What has been disclosed so far is the architectural concept, an indicative power density figure, and the three target markets. Product line-up, sampling timing and volume production timing were not given in this announcement.