AI Chip Performance Is No Longer Decided by the Node Alone
Coverage of AI accelerators gravitates to process node shrinks. What actually sets a GPU's bandwidth and power draw, however, is how the compute dies and memory are arranged, connected, and what they sit on — in other words, back-end packaging.
TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D technology that places multiple processor cores and high-bandwidth memory (HBM) stacks side by side on a single interposer, and it has become the backbone of AI accelerator performance (TSMC). Even with identical compute dies, a product cannot ship without CoWoS capacity. That is why, since 2024, supply constraints on AI silicon have so often been described not as a wafer shortage but as a packaging capacity shortage.
Advanced packaging is the umbrella term for this domain: 2.5D/3D integration, chiplets, high-bandwidth memory, and high-density substrates. This article is the entry point to the theme, surveying the technology, the bottleneck, and the supply chain across three layers, all from primary sources.
Why the Back End Became the Main Event
Scaling slowdown
Front-end scaling alone no longer delivers performance. Instead of one large die, small dies (chiplets) are connected at high density to accumulate performance.
The memory bandwidth wall
The more compute you add, the more memory bandwidth becomes the limiter. Only stacking HBM next to the compute die and linking it over a very wide interposer closes that gap.
Substrate and tool supply
Higher integration density raises the bar for substrates and equipment. Capacity additions in ABF substrates and hybrid bonding tools now set the ceiling on shipments.
None of the three is solved by "building it on a finer process." They moved outside the compute die, into the package — that is the shape of the late 2020s.
The Technology Landscape: Place, Stack, Bond
The field breaks down into three movements.
Place (2.5D). Represented by CoWoS, compute dies and HBM sit side by side on an interposer, connected over short, very wide paths. This is the standard configuration for today's AI accelerators, and TSMC plans to layer System-on-Wafer (SoW) and co-packaged optics (CPO) on top of it.
Stack (3D and HBM). Memory is moving fastest. SK hynix's HBM4 delivers twice the bandwidth and more than 40% better power efficiency than the previous generation, with mass production readiness announced (SK hynix). On the standards side, JEDEC's JESD270-4 specifies a 2,048-bit interface delivering up to 2 TB/s per stack (JEDEC), so bandwidth growth is designed hand in hand with packaging.
Bond (hybrid bonding). Copper-to-copper direct bonding without solder bumps shortens interconnect length and raises connection density. Applied Materials calls it a foundation for AI chips and went as far as taking an equity stake in tool maker Besi (Applied Materials). The more a design assumes chiplets, the more bonding accuracy translates directly into performance.
The Bottleneck Is Shifting to Substrates
The ABF capacity race
IBIDEN approved roughly JPY 500bn in capital investment across FY2026-FY2028. AT&S raised FY2026/27 CapEx guidance from EUR 400m to EUR 1.0-1.2bn. AI substrate capacity itself is the scarce resource.
The move to glass
Organic substrates are expected to reach their scaling limit around 2030. Intel unveiled glass substrates after a decade of R&D, and SKC completed the world's first mass-production facility in Georgia.
Substrates look unglamorous, yet this is the layer where supply is tightest right now. IBIDEN's board approved a three-year, roughly JPY 500bn IC package substrate investment plan for FY2026-FY2028 in February 2026 (IBIDEN). AT&S, centered on a new AI substrate line at its Kulim plant, raised FY2026/27 CapEx guidance from EUR 400m to EUR 1.0-1.2bn (AT&S).
Beyond that lies a change in the material itself. Intel holds that organic-based packaging will hit its scaling limit by the end of this decade and positions glass substrates as an indispensable route to extending Moore's Law past 2030 (Intel). SKC claims a 40% improvement in data processing speed over conventional substrates and has completed the world's first mass-production facility in Georgia (SKC). The realistic reading is a two-stage picture: an organic substrate capacity race through 2026, and a shift to glass around 2030.
Supply Chain and Policy: Capacity Is Booked Before It Exists
Advanced packaging has also moved to the center of sourcing-risk debates. The U.S. Department of Commerce finalized USD 1.4bn in awards under the CHIPS National Advanced Packaging Manufacturing Program (NAPMP), allocating USD 300m to advanced substrate and materials research and USD 1.1bn to operating a pilot facility (NIST). The EU Chips Act likewise names design, manufacturing, and packaging capacity explicitly, and the European Commission proposed Chips Act 2.0 in June 2026.
Tight supply shows up directly in OSAT investment decisions. In September 2026, Amkor announced phase 2 of its campus in Tempe, Arizona, raising planned investment to roughly USD 12bn (Amkor). The telling detail is that phase 1 cleanroom capacity was already oversubscribed by customer commitments before it came online. For chip customers seeking domestic supply, capacity is booked before it is built.
What to Check Next, by Role
- Design and technology planning: Do you commit to a chiplet-based design? Whether 2.5D is sufficient or 3D hybrid bonding is required changes your tool and partner choices.
- Sourcing: Are you looking only at wafer allocation? CoWoS capacity, HBM supply, and ABF substrates tighten independently, so lead times and second sources have to be secured separately for each.
- Materials and equipment makers: How do you split investment between organic substrate demand now and the glass ramp around 2030? The two differ in timing, not in whether they happen.
The common question is which layer holds the performance bottleneck. Tracking front-end scaling alone no longer explains either the supply or the performance of AI silicon.
Individual topics in this theme are covered in separate articles. For the substance of 2.5D integration, see CoWoS and Intel ASAT; for the memory side, see the HBM4 supply chain; for bonding, see the hybrid bonding tool race; for substrate supply and demand, see ABF substrate capacity plans and glass substrate mass production; and for policy and geopolitics, see the CHIPS Act and the EU Chips Act.