目录
01 为何散热设计成为瓶颈 02 热阻链与热界面材料的主导作用 03 液冷设计实践 04 封装架构对比 05 功率循环测试与可靠性裕量 06 布局设计与开关速度的权衡 07 参考事实卡片 为何散热设计成为瓶颈 SiC 功率器件的导热系数约为硅的三倍,结温额定值最高可达 200°C——与硅 IGBT 相比具有显著的先天优势。在等效条件下,开关损耗比 IGBT 低达 85%,意味着发热量本身已大幅减少。即便如此,散热设计执行不当仍会抹去 SiC 带来的全部性能优势。
原因直接明了。STMicroelectronics 明确指出,其 SiC MOSFET 的最高结温 200°C「仅受封装限制(limited only by the package)」,而非受半导体材料本身限制。若模块热路径不足,即便热输出低于等效 IGBT,结温依然会趋近其上限。SiC 导入失败的案例,集中于开关特性经过充分评估、而散热设计未获足够重视的情形。
> 来源:STMicroelectronics 公布,其 SiC MOSFET 最高结温 200°C「仅受封装限制」。STMicroelectronics — SiC MOSFETs
热阻链与热界面材料的主导作用 SiC 模块的热路径是串联热阻结构:结 → 壳 → 散热器 → 冷却液。根据 Wolfspeed 的测量与分析,热界面材料(TIM)在该路径中占总热阻的最高 60%。即便结壳热阻(RTHJC)控制在约 0.109 K/W,TIM 选型或涂覆质量不佳也会完全抵消这一优势。
TIM 的影响不止于设计阶段——在量产全过程中,它都是一个质量管控问题。涂覆厚度的偏差、气泡的夹入以及使用寿命内的老化,均会导致有效热阻上升。在量产中,TIM 涂覆工艺往往成为质量瓶颈。RTHJC 测量遵循 JEDEC 标准 JESD51-14 TDI(瞬态双界面)方法,该方法是验证与封装厂商公开规格符合性及来料检验标准的行业基准。
第二项考量是 CTE(热膨胀系数)匹配。SiC 芯片与基板材料之间的 CTE 失配产生热机械应力,在反复功率循环中导致 TIM 脱层与老化。在材料选型阶段确认 CTE 兼容性,是长期可靠性的前提条件。
液冷设计实践 开关损耗的大幅降低使 ROHM 指出,SiC 模块在部分应用中可将水冷和强迫风冷替换为自然对流冷却。工业低功率应用中已有无风扇设计的实证案例。然而对于高功率应用,液冷仍是主流,流量设计不足将导致无法实现预期的温度裕量。
在使用 CAB450M12XM3 的 Wolfspeed 30 kW 升压变换器设计参考中,需要 7.5 升/分钟 的冷却液流量,方能将结温维持在安全范围内。液冷设计需同时考量三个因素:流量、冷却液入口温度以及冷板热阻。流量不足会增加热阻,并引入瞬态电流峰值期间结温瞬时超限的风险。
封装架构对比 散热设计方案因封装架构差异而存在显著不同。目前实用化的封装形式主要有以下三种。
标准基板封装以单面方式安装于散热器,便于沿用现有机械设计与装配基础设施。但基板与 DCB 衬底之间的 CTE 失配是累积疲劳的根源,在高功率循环应用中,使用寿命可能成为制约因素。
顶面散热以 ROHM 的 TSC3PAK 为代表。其顶面散热结构省去了此前所需的 IMS(绝缘金属衬底),可直接安装于标准 FR4 PCB。ROHM 实测结果显示,在 11 kW 三相逆变器配置中损耗为 29.5 W,比同类器件的 33.3 W 低约 11%。若在系统层面(含装配成本)进行经济性评估,这是一个具备可行性的选项。
双面散热已在日本中小企业厅(隶属 METI)主导的 SAPOIN 项目开发中得到应用,实现了支持芯片结温 250°C 的薄型模块,采用风冷方式。然而,薄型复杂几何结构的树脂封装需要基于仿真的设计优化,量产门槛高于其他封装类型。
功率循环测试与可靠性裕量 功率循环(PC)测试是评估长期可靠性的必要手段。Wolfspeed 引用的典型测试条件为 ΔTj 75–125°C、Tj,max 125–175°C,失效判据定义为以下两者中先发生者:VDS 变化量 +5% 或 RTH 变化量 +20%。
测试形式分为 PCsec(导通时间超过 15 秒)和 PCmin(低于 15 秒),分别针对不同的退化机制。PCsec 中,热量穿透至基板和 DCB 衬底,整个焊接结构的疲劳为主要退化模式;PCmin 中,则以距芯片最近的焊接层为主。选取与实际应用工况相匹配的测试条件——如电动汽车驱动循环、逆变器启停频率等——直接决定测试对现场失效模式的复现程度。
Wolfspeed YM4 模块在相同封装尺寸下,功率循环性能达到竞争产品的三倍。对于要求长寿命与高可靠性的应用,定量的跨产品对比可为采购决策提供有据可查的依据。
布局设计与开关速度的权衡 Infineon 技术文档指出,PCB 布局不当会导致 SiC MOSFET 产生电压过冲,危及器件可靠性。SiC 开关速度越快,寄生电感的影响越显著,过压应力会加速栅氧化层的退化。
一项应对措施是增大栅极电阻以主动降低开关速度,但这会增加开关损耗并提高散热需求——形成直接的性能权衡。散热设计与布局设计以这种方式相互耦合;若任一方被推迟,最终将迫使两者重新来过。实际可行的做法是,从系统设计最早期阶段起,将 SiC 模块散热设计与布局设计及栅极电阻优化并行推进。
参考事实卡片
SiC thermal conductivity is about three times that of silicon and GaN.
onsemi material lists thermal conductivity of 4H-SiC at 4.9 W/cm°C, silicon at 1.5 W/cm°C, and GaN at 1.3 W/cm°C. SiC also has a bandgap of 3.26 eV, larger than silicon’s 1.12 eV.
Compared with silicon, 4H-SiC has about 10 times the dielectric breakdown field and about three times the thermal conductivity.
The material comparison table lists silicon dielectric breakdown field at 0.3 x 10^6 V/cm and 4H-SiC at 3 x 10^6 V/cm. Thermal conductivity is 1.5 W/cm°C for silicon and 4.9 W/cm°C for 4H-SiC. The energy gap is also 3.26 eV for 4H-SiC versus 1.12 eV for silicon.
SiC power devices can operate at junction temperatures up to 200°C.
STMicroelectronics SiC-based power devices can operate at junction temperatures up to 200°C, with the upper limit determined by package specifications rather than the device itself. Compared with the typical junction-temperature limit of conventional silicon devices, usually 150-175°C, SiC is much better suited to high-temperature environments. High-temperature tolerance enables simplified cooling systems and greater design flexibility.
The temperature limit of SiC devices is on the package side, not the semiconductor material itself.
According to STMicroelectronics, the 200°C operating-temperature limit of SiC power devices is constrained by package heat resistance, not by the physical limit of the SiC semiconductor material. This suggests that the SiC material itself has potential for even higher temperature tolerance. Advances in package technology may enable higher operating temperatures in the future.
ROHM SiC modules can reduce total switching losses by 85% compared with IGBT modules.
The material compares a 1,200 V / 100 A class 2-in-1 SiC power module with IGBT modules from three manufacturers. With an appropriate gate resistance, the SiC power module can reduce total switching losses, Eon + Eoff + Err, by 85% versus the lowest-loss IGBT module. The stated evaluation conditions include Vds = 600 V, Id = 100 A, Vg(on) = 18 V, Vg(off) = 0 V, Ta = 125°C, and an inductive load.
SiC power modules can make cooling systems smaller and lower-cost, and may replace water or forced-air cooling with natural cooling.
The material cites improved conversion efficiency from lower switching losses as a benefit of SiC modules. As a result, heat sinks and cooling systems can be made smaller and lower-cost, and in some cases water cooling or forced-air cooling may be replaced by natural cooling. Higher-frequency operation can also enable smaller passive components such as inductors and capacitors.
TIM is described as the largest thermal-resistance factor in a typical RTHJS stack, accounting for 60%.
In Wolfspeed’s illustrated example, the typical RTHJS distribution in a system application is TIM at 60%, DBC at 30%, heat sink at 4%, solder at 4%, and chip at 2%. Effective TIM thermal resistance is affected by bond-line thickness, thermal conductivity, surface area, and contact thermal resistance.
In Wolfspeed’s TDIM explanation, the example RTHJC value is 0.109 K/W.
The transient dual interface method is based on JEDEC JESD51-14 and identifies the branching point of the structure function from two step responses: a wet condition with TIM and a dry condition without TIM. In Wolfspeed’s example, 0.109 K/W is shown as the clearly separated point in the structure function and is used as RTHJC. A heating current of one-half to three-quarters of the module rated current is recommended.
CTE differences between SiC dies and baseplate materials can create thermomechanical stress.
The CTE of SiC die is 4.0 x 10^-6/K, while ceramic substrates are 4.5 x 10^-6/K for aluminum nitride and 8.2 x 10^-6/K for alumina. Typical baseplate materials have higher values, such as 16.5 x 10^-6/K for copper and 8.4 x 10^-6/K for Al-SiC composites, so material mismatch can cause solder fatigue and delamination. Wolfspeed describes WolfPACK as a design without a baseplate, enabling direct cooling of the DBC substrate.
The JEDEC JESD51-14 TDI method is the standard approach for measuring SiC MOSFET thermal resistance RthJC.
The transient dual interface test method defined in JEDEC Standard JESD51-14 is used to measure junction-to-case thermal resistance, RthJC, for SiC MOSFETs. The method heats the chip until junction temperature reaches steady state, then records the transient cooling curve to calculate thermal resistance. Comparing measurements under two interface conditions, good and poor thermal contact, separates package-internal thermal resistance.
In the TDI method, recording the transient cooling curve after steady state is the key step for calculating RthJC.
In JEDEC JESD51-14 TDI procedures, the chip is first electrically heated until junction temperature reaches steady state. Heating is then stopped and the transient cooling curve, or temperature-time response, is recorded with high precision. Analysis of this cooling transient derives the thermal structure function from junction to case and quantifies RthJC.
The same JEDEC measurement standard used for Si IGBTs is applied to thermal-resistance evaluation of SiC MOSFETs.
JESD51-14 was originally developed for silicon power devices, but it is also applied to thermal-resistance measurement of next-generation wide-bandgap devices such as SiC MOSFETs. Because SiC devices offer higher-temperature operation and higher heat-flux characteristics than silicon, steady-state conditions and cooling-curve analysis accuracy are especially important. ROHM has published technical material on applying this method to SiC MOSFETs.
In a 30 kW CAB450M12XM3 boost-converter example, a cooling flow rate of 7.5 lpm was required.
The application example is a 30 kW boost converter based on CAB450M12XM3, with overload of 50 kW for 0.1 seconds, switching frequency of 20 kHz, duty ratio of 0.5, coolant temperature of 25°C, and allowable temperature rise of 85°C. Wolfspeed SpeedFit 2.0 calculated total losses of 295.55 W at 30 kW. Meeting the conditions required cold-plate thermal resistance of 0.008°C/W, corresponding to a 7.5 lpm flow rate, with maximum junction temperature including overload of 107.69°C.
Typical power-cycling test conditions use ΔTj of 75-125°C and Tj,max of 125-175°C.
Wolfspeed presents typical power-cycling test profiles with junction-temperature swing ΔTj of 75-125°C and maximum junction temperature Tj,max of 125-175°C. Pulse width is shown as less than 5 seconds for PCsec and more than 15 seconds for PCmin.
Wolfspeed uses VDS +5% and RTH +20% as failure criteria in power-cycling tests.
Wolfspeed’s power-cycling test aligns with the AQG324 automotive standard and monitors two main failure modes. The first is a 5% increase from the initial drain-source voltage VDS required to maintain load current, and the second is a 20% increase in thermal resistance RTH.
PCsec and PCmin evaluate different degradation mechanisms, with 15 seconds as the boundary.
PCsec testing uses pulses of a few seconds and mainly evaluates thermal stress near the top-side die interconnect and die attach. PCmin testing uses pulses longer than 15 seconds to several minutes, allowing heat to penetrate deeper into the substrate layers and more strongly evaluate solder joints, baseplates, and package joints.
Wolfspeed’s YM4 shows three times the power-cycling performance of competing devices with the same footprint.
Wolfspeed describes its YM4 power-module family as using copper-clip technology, sintered die attach, and epoxy encapsulation. The company says this enables three times the number of power cycles compared with best-in-class competing devices in the same footprint.
ROHM’s TSC3PAK is a top-side cooling package for SiC MOSFETs.
ROHM developed TSC3PAK to improve thermal characteristics and mechanical durability compared with conventional bottom-side cooling packages. TSC3PAK uses a thick copper frame to improve heat spreading and reliability.
TSC3PAK eliminates the need for IMS substrates and enables use of standard FR4 PCBs.
Conventional BSC structures required insulated metal substrates to strengthen the thermal path of the PCB. In TSC3PAK, the device case is placed in direct top-side thermal contact with the heat sink through a thermal interface material, enabling use of standard FR4 PCBs.
In an 11 kW three-phase inverter simulation, TSC3PAK losses were 29.5 W versus 33.3 W for Device A.
The case study covered an 11 kW two-level three-phase inverter with a 920 V DC link and 20 kHz switching frequency. The simulation used PLECS with RthJH and switching-loss values obtained from double-pulse testing. The resulting total power loss was about 29.5 W for TSC3PAK and 33.3 W for Device A.
A double-sided cooling SiC power module was developed to support a 250°C device junction temperature with air cooling.
The project aims to develop a thin, high-current SiC power module with a double-sided heat-dissipation structure that can maintain a device junction temperature of 250°C using only air cooling with a fan. TJ = 250°C far exceeds the typical limit of silicon devices, usually 150-175°C, and uses SiC material properties to the fullest.
Thin double-sided cooling modules require simulation-based design for resin encapsulation.
Because the module structure is thin and complex, uniformly filling the narrow internal spaces with encapsulation resin is a manufacturing challenge. To solve this, the design uses simulation-based module-structure design, or resin-flow analysis. Poor resin filling can lead directly to voids and dielectric breakdown, making this process essential for manufacturing yield.
Improper board layout can cause voltage overshoot in SiC MOSFETs and undermine device reliability.
Infineon evaluation material identifies poor layout design as a risk that can cause voltage overshoot in SiC MOSFETs. Overshoot may exceed the device absolute maximum ratings and lead directly to failure modes. Because this risk stems from SiC’s fast switching and steep dv/dt, minimizing PCB trace parasitics and parasitic inductance is an essential design requirement.
Intentionally slowing switching speed to compensate for poor layout increases losses and cooling requirements.
Infineon material notes that voltage overshoot is sometimes mitigated by intentionally slowing switching speed, for example by increasing gate resistance. This measure raises switching losses and increases heat-dissipation requirements for heat sinks and cooling systems. As a result, SiC’s original advantages in high efficiency and high-frequency operation are partially lost.