Toshiba Begins Test Sample Shipments of 1200V SiC MOSFET 'TW007D120E' — Rds(on)×Qgd Figure of Merit Improved by Approx. 52%, Targeting Next-Generation AI Data Center Power Supplies

Toshiba Device & Storage began shipping test samples of the TW007D120E, a 1200V trench-gate SiC MOSFET targeting power supply systems for next-generation AI data centers, on May 20, 2026. Mass production is being prepared for fiscal year 2026, with deployment in renewable energy equipment also anticipated.

Technical Significance of the ~52% Improvement in Rds(on)×Qgd

The core performance improvement in the TW007D120E is an approximately 52% reduction in the figure of merit (FOM) Rds(on)×Qgd compared to the current product. This FOM represents the product of on-resistance (Ron) — an indicator of conduction loss — and gate-drain charge — an indicator of switching loss — capturing the traditional trade-off where reducing one tends to increase the other. Toshiba has relaxed this constraint simultaneously through improvements to the trench-gate structure, enabling reductions in both conduction loss and switching loss relative to previous devices.

1200V Rating and AI Data Center Power Architecture

AI data center power supplies require high-voltage switching devices in the conversion stages from the ±400V HVDC bus to server racks (PFC, LLC, phase-shift full bridge, etc.). While ROHM's SCT4013DLL (750V) targets BBU applications directly connected to the ±400V HVDC bus, the TW007D120E's 1200V rating is intended for applications requiring greater insulation design margin and improved efficiency in voltage conversion stages. Device makers are accelerating the build-out of SiC lineups across voltage tiers, and designers are increasingly selecting devices on both voltage class and loss characteristics.

Key Points for Design Engineers

Since the device is at the test sample stage, confirming any performance differences from mass-production units and manufacturing yield data is a prerequisite for procurement decisions. The 52% FOM improvement is a nominal value at the rated operating point; actual improvement depends on gate driver circuit design, switching frequency, dead-time settings, and temperature conditions. Early characterization via double-pulse testing on an evaluation board under application-specific conditions is recommended. Toshiba is also considering availability in the QDPAK package suited for high-current mounting, making it advisable to finalize PCB design direction — including package selection — at an early stage.